Altium

Design Rule Verification Report

Date:		10/20/2020
Time:		7:19:46 AM
Elapsed Time:		00:00:02
Filename:		C:\Users\jq080021\OneDrive - Qorvo\DXP\DXP_2020\PAC5526EVK1_RevA\PAC5526EVK1_RevA.PcbDoc

Warnings:		0
Rule Violations:		0

Summary

Warnings	Count
Total	0

Rule Violations	Count
Clearance Constraint (Gap=6mil) (All),(All)	0
Clearance Constraint (Gap=10mil) (InNamedPolygon('AIO10') Or InNamedPolygon('U_OUT') Or InNamedPolygon('AIO32') Or InNamedPolygon('W_OUT') Or InNamedPolygon('V_OUT') Or InNamedPolygon('AIO54') Or InNamedPolygon('VIN')),(All)	0
Short-Circuit Constraint (Allowed=No) (All),(All)	0
Un-Routed Net Constraint ( (All) )	0
Width Constraint (Min=8mil) (Max=100mil) (Preferred=10mil) (All)	0
Power Plane Connect Rule(Direct Connect )(Expansion=20mil) (Conductor Width=10mil) (Air Gap=10mil) (Entries=4) (All)	0
Minimum Annular Ring (Minimum=5mil) (All)	0
Hole Size Constraint (Min=10mil) (Max=246mil) (All)	0
Hole To Hole Clearance (Gap=8mil) (All),(All)	0
Minimum Solder Mask Sliver (Gap=0mil) (All),(All)	0
Silk to Silk (Clearance=0mil) (All),(All)	0
Net Antennae (Tolerance=50mil) (All)	0
Height Constraint (Min=0mil) (Max=1000mil) (Prefered=500mil) (All)	0
Total	0