In the rapidly evolving landscape of digital storage, Solid State Drives (SSDs) have emerged as a pivotal technology reshaping how data is stored and accessed. SSDs have become more popular than hard disk drives (HDDs) because they are more reliable, faster, use less power, perform better and are lighter and smaller.

The SSD market is expected to reach $67 billion by 2028. A significant part of this market includes the hardware, firmware, and software for Power Loss Protection (PLP), which is essential for keeping SSD systems running normally after a power outage.

This article delves into the intricate world of SSD technology, exploring its benefits and the transformative impact it has on computing environments. Additionally, we'll cover recent advances in SSD technology, including Power Management Integrated Circuits (PMICs) and PLPs and their roles in enterprise data storage.

A Look at the Power Loss Protection in SSDs

In the rapidly evolving digital storage landscape, SSDs are crucial in transforming how we save and retrieve data. Enterprise data storage systems are used by large businesses to handle, save, and secure important data for activities like cloud computing, data mining, and online transactions. These systems are set up across data centers.

As Figure 1 shows, the PLP in SSDs offers sufficient energy to save critical data to the NAND during a power outage (The NAND flash memory is a type of non-volatile storage technology that does not require power to retain data). These PLP systems have been around in the SSD marketplace for a while, playing a vital role in keeping data safe if the power goes out. The PLPs main task is to extend the operation of the SSD to securely move data from the drive's temporary storage to its permanent memory, ensuring the data is still there and accessible after the system powers back on. The PLP system does this by using special capacitors to keep the SSD powered long enough to ensure that all data in the cache is saved to NAND flash memory and the directories are updated.

 

 

Figure 1: Shows the extension of power using PLP.

 

These capacitors, as shown in Figure 2 below, hold enough energy to keep the SSD running while it backs up data after power is lost. This energy provides additional runtime to allow the system to finish writing data to the memory after a power failure. Also, some SSDs use special software rules to control how data is written when power is lost, keeping the data safe and reducing the chance of errors. For guidance on how to choose and configure these capacitors based on workload and holdup requirements, please refer to our application note PLP Capacitor Selection and Configuration.

Let’s take a quick look at the main components of an SSD. Figure 2 shows the standard components of an SSD used in data centers.

 

 

Figure 2: The standard components of an enterprise SSD.

 

Like many system upgrades, these PLP capacitors and software additions need space and engineering design effort. They also use varying amounts of energy, depending on the SSD design and cache size, but the benefits they offer to businesses and data centers are substantial.

Another key development in the SSD marketplace has been the introduction of PMICs. These PMICs optimize the power delivery architecture and SSD performance. Let’s explore this new development further and the benefits it provides.

Integrating the PMIC and PLP

Incorporating PMICs into an SSD offers engineers significant advantages for their designs. PMICs offer a variety of voltage regulators, programmability, sequencing and monitoring capabilities. However, the standard SSD design still requires the need for two separate functional integrated circuits – the PLP and PMIC. To reduce solution size, design time and the need for a separate PLP monitoring/controlling integrated circuit – these components can be combined, as shown in Figure 3 below. By combining these two components on one integrated circuit, SSDs can be made more compact than traditional designs.

 

 

 

Figure 3: Integrating the PMIC and PLP into one IC package.

 

When integrating the components from Figure 3 into a single chip, we create a comprehensive solution that includes PLP capacitors and a PMIC to monitor and boost system-level performance. Moreover, the PMIC provides optimum output voltages, allowing the SSD to reduce power consumption. See below Figure 4.

 

  Figure 4: SSD with a PMIC and integrated PLP added on board.

 

Qorvo’s ACT85611 & ACT85411

PLP is a common feature in Qorvo’s ACT85611 and ACT85411 as shown in Figure 4 below. Each device's PLP includes an eFuse and back-to-back MOSFETs for bi-directional isolation between the input and output. This setup safeguards the device during hot swaps and controls inrush current. A blocking MOSFET, positioned after the eFuse, separates the input bus from the Buck/Boost regulator and the storage capacitor, ensuring normal operation even if the capacitor fails. This MOSFET also enables low current charging of the capacitors during startup. Normally, with a stable power source, the Buck/Boost regulator operates as a boost regulator, charging the capacitors to a voltage higher than the input. In case of power loss, the regulator switches to Buck mode to draw energy from the capacitors to power the system. An analog-to-digital converter (ADC), along with a capacitor health monitoring system, checks voltages, currents, temperatures and capacitor condition for reliable operation.

 

 

Figure 5: Block diagrams of ACT85611 & ACT85411.

 

The  features of Qorvo’s PMIC devices vary to cater to diverse system requirements. The ACT85611 includes four efficient buck regulators (three 4 A and one 2 A) with output voltages from 0.6 V to 5.26 V, a low current buck regulator (Buck VCC) for internal circuitry and external loads up to 100 mA, an LDO with 300mA capacity and adjustable voltage from 0.6 V to 3.75 V, and a 1 A boost regulator offering 10.8 V to 13.2 V output. The ACT85411 features two 10A buck regulators with a 0.6 V to 5.26 V output range, a low current 5 V fixed buck regulator (VCC5) for internal and external loads up to 200 mA, and a 1 A buck-boost regulator with a 9.6 V to 16 V output range.

Comparing the ACT85611 & ACT85411

Both devices have the essential features for power loss protection. However, the ACT85411 offers additional enhancements, as detailed in Table 1. The PMIC specifications vary between the two, enabling them to cater to specific types of systems.

 

 

 

Table 1: Comparison of ACT85611 and ACT85411.

 

A Final Word

SSDs are revolutionizing the data storage industry with their superior reliability, speed, power efficiency, compactness, and light weight. Central to this transformation is the integration of PLP and PMIC, ensuring data integrity during power outages and enhancing device performance. This article highlighted the significance of PLP in preserving data in SSDs by maintaining power through special capacitors and software protocols during outages. It also explored the advancements in PMIC technology, notably in Qorvo’s ACT85611 and ACT85411 devices, which offer comprehensive power management solutions tailored to diverse system requirements. These devices feature PLP control circuitry, efficient buck, boost and buck-boost regulators and LDOs, providing a cost-effective, feature rich power solution for reliable SSD operation in enterprise data storage systems.

For readers who would like to take a deeper dive into PLP control states, sequencing and system-level behavior, Qorvo's Power Loss Protection System Guide provides a detailed walkthrough of the full protection architecture. For more on this topic and solutions for your latest design challenge, visit the  Qorvo Design Hub for a rich assortment of videos, blog articles, white papers, tools and more. For more information on this and other Qorvo power management PLP design please visit Qorvo.com or reach out to Technical Support.

About the Authors

Our authors bring a wealth of technical expertise in developing and optimizing power solutions for advanced technologies. With a deep understanding of customer needs and industry trends, they collaborate closely with our design teams to drive innovation and deliver cutting-edge solutions that support industry-leading products.

Thank you to our main contributors to this article: Dexter Semple (Staff Power Management System Engineer), David Schnaufer (Technical Marketing Manager) and Michael Day (Sr. Manager Applications Engineering).