August 23, 2018

    This blog post was first published by United Silicon Carbide (UnitedSiC) which joined the Qorvo family in November 2021. UnitedSiC is a leading manufacturer of silicon carbide (SiC) power semiconductors and expands Qorvo's reach into the fast-growing markets for electric vehicles (EVs), industrial power, circuit protection, renewables and data center power.

    By Zhongda Li, Staff R&D Engineer

    There's no beating the laws of physics. Resistors are going to dissipate electrical energy as heat and drop voltages. Capacitors will take time to store charge, and time to release it. Inductors will take time to create and collapse electromagnetic fields. There's nothing we can do about it, so electronics designers have, since the days of thermionic valves, learned to work around these factors by developing clever circuit topologies. It turns out that, physics being physics, what worked for valves is equally applicable to today's high-performance semiconductors.

    How Miller capacitance limits high-frequency amplification

    Take, for example, the Miller effect. In the 1920s, US electrical engineer John Milton Miller identified an issue with simple triode vacuum tubes when used as amplifiers, due to the internal capacitance between the grid and anode. This capacitance reduced the bandwidth of the amplifier by imposing an increasing amount of negative feedback as the capacitance's impedance fell with rising operating frequencies.

    Miller realized that connecting two triodes in series as in Figure 1 (a CASCaded triODE, or cascode topology) would cut the total capacitance from input to output. The upper triode's cathode voltage is controlled by the lower triode, given that the upper tube grid is at a fixed voltage. When tetrodes were developed with internal screens, this internal capacitance and its related effect were reduced, making it possible to build single-tube amplifiers that would operate at hundreds of megahertz.

    figure 1
    Figure 1: The original CASCaded triODE – or cascode – circuit

    The return of the Miller effect

    The Miller effect returned as designers started replacing thermionic valves with solid-state semiconductors, and this started to restrict high-frequency operation once again.

    Why so? In a MOSFET-based switching circuit, the Miller effect limits switching speed because the drive circuit has to charge and discharge the input capacitance in a reliable and low-loss way. The effect of this Miller capacitance, designated CGD, varies, depending on the gate voltage.

    Consider, for example, an enhancement-mode MOSFET switch that is Off when its gate is at 0 V. The total gate-input capacitance appears as a network (see Figure 2), which includes CGS, CGD, CDS, the load ZL and bulk capacitance CBULK. There is also a positive voltage across CGD. When the MOSFET is turned On, the drain voltage falls to almost zero and the total capacitance becomes CGD in parallel with CGS, with a negative voltage across CGD when compared with the Off state. In switching from On to Off and back, the input capacitance must swap between these conditions.

    figure 2
    Figure 2: The equivalent input capacitance of a MOSFET when Off and On

    The plateau in the positive-going part of a MOSFET gate-switching waveform (see Figure 3) represents the transition between the two input capacitance states as the driver suddenly has to work harder, making the switching transition slower. To make the effect worse, as the drain drops in voltage, it tries to 'push' the gate negative through CGD, fighting the positive On-voltage command. This process is reversed when driving the MOSFET Off. CGD tries to 'pull' the gate positive, which is why designers working with MOSFETs and IGBTs are encouraged to use a negative Off-state gate voltage to counter the effect. This, in turn, increases the power needed to drive the gate.

    figure 3
    Figure 3: Miller capacitance 'plateau' on gate drive voltage

    Controlling gate-drain capacitance

    The gate-drain capacitance, CGD, of a device is influenced by the architecture of the semiconductor device, and so varies depending on whether it has been built laterally or vertically. It's possible to minimize CGD for low-voltage MOSFETs, but it can become an issue at high voltages, especially when designers want to build wide band-gap devices using materials such as silicon carbide (SiC) or gallium nitride (GaN). There's no getting around the physics: the switching speed of these technologies is still limited by their Miller capacitances, and the best way to counter that effect is to use a cascode circuit topology.

    The modern cascode

    LINKS NEEDED A basic SiC switch uses a junction FET (JFET) architecture. If the JFET is constructed as a vertical device, its CGD can be advantageously low, and its drain-source capacitance CDS can be lower still. However, a JFET is a normally-ON device with its gate at 0 V, and needs a negative gate voltage to be switched Off. This is an issue in a bridge circuit, in which all the devices default to the On state the instant power is applied. It would be better to build such circuits using a normally-OFF device, which can be achieved by arranging a Si MOSFET and a SiC JFET in a cascade topology (Figure 4).

    figure 4
    Figure 4: The Si/SiC cascode

    When the MOSFET gate and source are at 0 V, its drain voltage rises. The JFET gate is also at 0 V so when the voltage on its source, from the MOSFET drain, rises to 10 V, the JFET sees a negative voltage of -10 V between its gate and source and so switches Off. When the MOSFET gate goes positive, it turns On and so shorts the gate-source of the JFET, switching the JFET On. This circuit topology creates the desired normally-OFF device with 0V on the MOSFET gate. The topology also means that the series input-output capacitance includes CDS for the JFET, which is close to zero, reducing the Miller effect and its impact on high-frequency gain.

    Other advantages

    While switching, the Si MOSFET drain voltage is a 'pot-down' of the JFET drain voltage through the almost-zero drain-source capacitance CDS of the JFET and the non-zero CDS of the MOSFET, so the MOSFET drain stays at a low voltage. This means that the MOSFET can be a low-voltage type with a very low On-resistance between drain and source and much easier gate-drive characteristics. As a further advantage, the body diode of a low-voltage MOSFET can have a very low forward drop and fast recovery. The JFET has no body diode, so when third-quadrant, reverse-switch conduction is necessary, as in commutating-bridge circuits or synchronous rectification, the MOSFET body diode conducts. This clamps the JFET gate-source to about +0.6 V ensuring it is turned On hard, which in turn enables a reverse current to flow with a low voltage drop.

    The end of the Miller effect

    The SiC cascode topology solves the Miller capacitance problem in a way that also gives easy gate drive, normally-OFF operation and a high-performance body diode. This is unlike SiC MOSFETs, in which the characteristics of the body diode can be poor, or even GaN HEMTs, which can have high CDS. The immutability of physics, which led to the high-frequency gain-limiting Miller effect in thermionic devices, also applies to semiconductor devices. That very same immutability, though, also means that a cascode-based solution to the problem works as well in a modern SiC device as it did in an old-fashioned valve. The more things change, it seems, the more they stay the same.

    More information about UnitedSiC and the benefits of using cascodes is available here.


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