August 2, 2018
This is the second blog in a three-part series explaining various aspects of electrostatic discharge (ESD) and system-level ESD design for mobile devices.
In Part 1, we introduced the basic concepts
of ESD and system-efficient ESD design (SEED). This blog gives you all
the necessary pieces you should have in your toolkit for SEED. Part 3 will
cover how to use SEED methodology along with modeling and simulation to
optimize your system-level handset designs.
To refresh, SEED is…
…a co-design methodology that comprehends both on-board and on-chip ESD protection to analyze and achieve system-level ESD robustness. This approach requires a thorough understanding of the interactions between external ESD pulses, full system-level board design, and device pin characteristics during an ESD stress event.
As a general strategy, you can use a number of protection components on the PC board to protect the end-product from an ESD event. These protection components can include the following:
Passive and active components, like:
However, there are several things to keep in mind when using these components:
But beware: Capacitance of the off-chip protection device will cause mismatches in the RF pathway. To compensate for these mismatches, designers need to adjust their matching networks in the RF and antenna paths.
Glossary of Terms
TVS diodes are one of the go-to components for ESD protection. They operate by shunting excess current when the induced voltage exceeds the avalanche breakdown voltage. They are a clamping device, suppressing all overvoltages above the breakdown voltage. They automatically reset to the off state when the overvoltage goes away but absorb much more of the transient energy internally.
A TVS diode may be either unidirectional or bidirectional. A bidirectional diode can be represented by two mutually opposing avalanche diodes in series with one another, as shown below, and connected in shunt configuration relative to the pin to be protected. These devices are manufactured as a single packaged component.
For ESD protection in RF applications, it’s mandatory to keep the TVS diode capacitance as small as possible. This avoids a detuning of the input matching, and as a result, the protection device will create less harmonic distortion.
The following figure shows the current-voltage (I-V) curve of a bidirectional TVS diode. As you can see, the TVS is symmetrical with respect to the origin, and its ESD protection capability is provided for a positive and negative ESD strike.
The following graph compares the residual voltages of a varistor, polymer and TVS diode in response to an ESD strike. As you can see, today’s silicon-based TVS diodes are the most effective approach to ESD strikes.
However, where you place the TVS makes a big difference. ESD protection won’t be as effective if you don’t design the circuit properly. Keep in mind these general guidelines:
So what is the proper placement? As shown in the following image, you should:
To mitigate ESD events, it’s essential to properly ground every aspect of the finished end-product — the PC board, all IC chips and components, the housing, cover, etc. Make sure you consider all the following aspects in your end-product’s grounding:
Understanding primary and secondary ESD protection is a fundamental part of SEED methodology. Typically:
Co-design of the primary and secondary ESD protection stages is the fundamental concept of SEED methodology.
The following figure shows a high-level, basic view of the primary and secondary clamp for ESD protection in an RF front end (RFFE).
Note: Some system designs require an additional on-board secondary clamp located before the IC to mitigate any residual ESD charge a component pin might see.
Let’s look a bit closer at primary and secondary protection:
Co-design of the primary and secondary ESD protection stages — that is, of the on-board and on-chip protection — is the fundamental concept of SEED methodology. These two stages provide the necessary protection where the current-carrying capabilities on both branches are balanced by a serial impedance.
Simulating and analyzing the two protection stages helps board designers select the proper on-board protection clamping levels, to ensure peak residual pulses reaching the ICs are effectively handled. SEED protection design using simulation requires putting together International Electrotechnical Commission (IEC) stress models, TVS and IC interface pin models based on SEED parameters, and an isolation impedance circuitry (i.e., on the PC board). We'll go into the details of how to simulate and analyze your design for SEED in Part 3.
Different applications will have different demands for ESD protection. One approach might be good enough for your application, but it may not work for others. Ultimately, the design you use has to pass FCC and IEC testing, so that your product can be certified and sold.
Let’s look at several strategies you could employ for ESD protection in the RFFE.
The most basic approach uses a shunt inductor. As shown in the following figure, the inductor (L) is the main shunt element for the ESD current pulse. This inductor should be in the low nano-Henry range (<20 nH) to be an effective ESD protective solution. However, it does add insertion loss, which creates some RF performance challenges. A shunt capacitor is typically introduced for RF matching purposes, not ESD protection.
A second approach uses a single-stage high pass filter (HPF), as shown in the figure below. However, this may not be the most effective approach.
A third approach uses two stages of ESD protection, as shown in the next figure. This approach uses a TVS as primary protection and an HPF for secondary ESD protection to capture the residual stress.
As you can see from the image below:
Ultimately, you’re trying to reduce the voltage that the IC would see in an ESD strike; the goal is to reduce all the peak voltages before they hit the IC. We believe an ideal ESD strategy is the two-stage approach, with the first stage using a TVS element (TVS diodes) and the second stage using an HPF network.
It isn't uncommon to have ESD problems late in the design cycle when the mobile device doesn’t pass certification tests. We’ve learned that the best approach is to plan for ESD protection and the RF design from the outset — before designing the full board — because it reduces churn, design spins and certification headaches.
Now that you have the background and the tools to address ESD, our last blog in this series will talk about SEED methodology in detail and how you can incorporate it
into your system-level designs.
Read all the blogs in our series about overcoming ESD challenges in mobile devices:
Have another topic that you would like Qorvo experts to cover? Email your suggestions to the Qorvo Blog team and it could be featured in an upcoming post.