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    Can the drain dV/dt be controlled by the gate resistor?

    Yes. For hard-switching, the turn-on dv/dt slope can be effectively controlled by gate resistance. The turn-off requires higher gate resistance to slow down. But we recommend using a small RC snubber across device drain-source to achieve high efficiency and low EMI at same time. For more details, please see our webinar on this topic.

    Why do Qorvo SiC FETs use the cascode technology instead of the MOSFET technology? Is the cascode a transition product and will it move to a MOSFET at Qorvo?

    Qorvo has focused on SiC JFET based cascodes due to the excellent properties of the cascode device from ease of gate drive, good body diode behavior to good short circuit handling. The key to the cost-performance benefit comes from the low RdsA of SiC vertical JFET compared to SiC Planar and Trench MOSFETs. This is because the channel region in MOSFETs becomes a greater contributor to device RdsA. We see that this difference will remain as both JFET and MOSFET technologies advance, both at 1200 V and even more so at 650 V. With the release of stacked cascode chips in 2019, the assembly of Qorvo cascodes becomes equivalent to SiC MOSFETs in complexity. With these improvements, we see cascodes as a long term solution for power electronics needing the benefits of wide band gap (WBG) switches.

    How are Qorvo SiC FETs different than GaN cascodes?

    The Qorvo FET uses a vertical SiC JFET with much lower RdsA than lateral GaN FETs, even at 650 V. It can also be extended to much higher voltage ratings. The cascode device also uses a specialized custom LV MOSFET to simplify FET operation and offer gate drive compatibility with all existing SiC MOS and Si IGBT/MOS switches. The main structural reason that Qorvo SiC FETs are superior stems from the JFET structure with Cds=0, which eliminates the voltage divider problem during fast switching that affects the GaN cascode, and previous SiC cascode attempts.

    What challenges had to be solved in the commercialization of SiC cascode technology?

    The SiC MOSFET structure is quite familiar to most power supply and inverter designers, as well as device manufacturers. The SiC JFET is quite different to process, and creation of cascode products require more engineering effort, including special LV Si MOSFETs and advanced packaging. Qorvo is among the few manufacturers with all the required packaging, Si and SiC expertise in one team to accomplish this. Finally, SiC MOSFETs are easier to control with gate resistors, while SiC cascodes have a limited control range, requiring the Qorvo approach of application tailored devices. These devices then offer best-in-class performance.

    Are there any limitations or guidelines for Cascodes/FETs being used in a parallel application?

    Qorvo Cascode/FETs are commonly used in parallel to increase power output. The performance of the FET is dominated by the SiC JFET. That controls the switching speed and provides a device where Vth does not decrease with temperature and has a strong positive temperature coefficient of Rdson. These characteristics allow the device to paralleled very effectively, and de-sensitize it to variations in the low voltage MOSFET Vth etc.

    When using the cascode FET, how do you make sure the LV MOS will not experience overstress?

    The key to avoiding voltage over-stress in the LVMOS is to use a JFET device structure with Cds=0, to avoid any capacitive voltage divider behavior. Furthermore, the LVMOS is designed with a built-in clamp PN junction diode in each cell of the trench MOSFET which allows the device to tolerate large repeated avalanche events indefinitely. This is proven both by avalanche mode burn-in, as well as exposure to 1M cycle avalanche events with no parametric shifts.

    How do you adjust the turn on/off speed in the cascode FET?

    For the SIC Cascode FET, turn-on speed can be increased by using higher Vgs(on), or lower Rgon. The device turn-on can be slowed with higher Rgon, lower Vgs(on). The turn-off is harder to adjust with Rgoff, although higher Rgoff will in fact slow down the device. It is better to use a small RC snubber, either on the DC bus, or across the device, to minimize overshoots and ringing with much lower degradation in switching loss. Recommended snubber guidelines for our different SiC FETs can be found in two documents:

    The SiC JFET die size is small. How does it manage its avalanche capability compared to a SiC MOSFET?

    The Eas capability of a SiC device will indeed depend on die size. However, in practical applications, what is more important is the ability of the device to handle high peak currents of low energy avalanche, which can occur during lighting strikes and other overstress events on the AC line. In this area, the SiC Cascode FET from Qorvo is excellent, because of the mechanism by which the JFET handles the avalanche by going into the active mode. Very high avalanche current density can be handled safely in repetitive mode, without any shift in device parameters and capacitances, much better than with traditional SiC MOSFETs where the gate oxide can be impacted./

    For your SiC cascode FETs, what is the maximum operating frequency that is recommended (based on conduction loss + switching loss, maximum efficiency)?

    Maximum operating frequency depends on the type of hard or soft switching being used. Due to high Eon losses in all switch devices, hard switching frequencies are kept below 100-200 kHz. For soft switched circuits, 650 V SiC cascode FETs are in use at 500 kHz. 1200 V FETs can also be used at 200-500 kHz, although most high efficiency circuits use lower frequencies.

    Why is the SiC MOSFET Rdson vs temperature curve flatter than SiC cascode FETs?

    The SiC MOSFET channel mobility is quite low, and its temperature dependence results in a decrease of channel resistance with temperature between 27 degrees C and 125 degrees C. This compensates the increase in drift layers resistance with temperature as is common for all ideal bulk conduction. The SiC JFET structure has a bulk channel with 10-20X higher mobility, and which leads to the lower RdsA. This mobility increases with temperature more in line with ideal bulk mobility. This makes the overall increase of Rds with temperature greater for SiC cascode FETs. This makes the devices easier to parallel, and make it easier to realize robust short circuit handling capability.

    Why does Qorvo SiC FET's Qrr increase very little over temperature (10% from 25 degrees C to 150 degrees C)?

    This is because for Qorvo SiC FETs, most of the Qrr comes from the capacitive charge SiC JFET Coss. Since it is a capacitive charge, it does not increase with temperature. A very small portion of the Qrr comes from the LV Si MOSFET body diode, which does increase with temperature. So the overall effect was only 10% increase, very small.

    In Qorvo SiC FET datasheets, you recommend using a large Rg of 20 ohm for turn off. Why is that?

    This is because the Qorvo SiC FET has very small Cgd, so it tends to turn off very fast, which also gives very low turn-off loss. So using around 20 ohm Rg,off, the FET turn-off can be slowed down to dv/dt of about 80 V/ns, which is still quite fast, and gives very low turn-off loss. So basically turn-off losses which are same or better than conventional SiC MOSFETs can be achieved using a 20 ohm Rg,off.

    What is the terminal finish for D2-PAK? On the TO-247, TO-220, and D2-PAK, what is the finish of the drain tab (backside)?

    All are pure tin plated.

    Is a snubber a necessary circuit when using an SiC FET?

    The Qorvo fast SiC FET series (UF3C/UF3SC) often need at least a bus snubber, and in cases of poor layout or when using 3L packages, they may require an RC snubber across the device. This user guide shows the appropriate gate resistors and snubbers we recommend.

    Do you support LTSPICE and where is that information?

    Yes, we support LTSPICE. From our website, you can download the LTSPICE models and an application note with instructions and recommendations for using the models.

    What's the difference between the UJ3C and UF3C SiC FET devices?

    The UJ3C FET series are our 3rd generation SiC FETs that are more of a general use component. These parts are great for soft switching applications where hard turn-on losses need not be minimized.

    The UF3C FETs are designed for hard-switched, fast turn-on applications. This series offers lower Qrr and lower Eon compared to the UJ3C series. These components are quite fast and often a small device snubber is recommended to achieve very low losses with clean waveforms. More information to support higher-performance UF3C-based designs is available here.

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